A 1.6GHz/4.8GHz dual-band CMOS fractional-N frequency synthesizer for S-Band radio applications

Author

Bajestan, Masoud Moslehi ; Foli, Eugene ; Hedayati, Hajir ; Entesari, Kamran

Author_Institution

Analog & Mixed Signal Center, Texas A&M Univ., College Station, TX, USA

fYear

2014

fDate

1-3 June 2014

Firstpage

429

Lastpage

432

Abstract

A 1.6 GHz/ 4.8 GHz fractional-N frequency synthesizer in 0.18-μm CMOS technology is presented in this paper. Its purpose is to generate the local oscillator (LO) signals for a fully integrated S-Band transceiver with a direct-conversion receiver (RX) and a dual up-conversion transmitter (TX) to avoid the frequency pulling problem. The synthesizer achieves phase noise of -141.3 dBc/Hz at 1.62 GHz and -132.6 dBc/Hz at 4.86 GHz (both at 3 MHz offset), with reference spurs <;-70.2 dBc for the lower band (LB) and <;-63.8 dBc for the higher band (HB). Total power consumption is 18.2-22.7 mW from a 1 V supply for the VCO and 1.8V for the other synthesizer blocks.

Keywords

CMOS analogue integrated circuits; MMIC oscillators; UHF integrated circuits; UHF oscillators; field effect MMIC; frequency synthesizers; radio transceivers; voltage-controlled oscillators; CMOS technology; S-band radio; VCO; direct-conversion receiver; dual up-conversion transmitter; dual-band CMOS fractional-N frequency synthesizer; frequency 1.6 GHz; frequency 4.8 GHz; frequency pulling problem; fully integrated S-Band transceiver; local oscillator signal generation; power 18.2 mW to 22.7 mW; size 0.18 mum; voltage 1 V; voltage 1.8 V; CMOS integrated circuits; Dual band; Frequency synthesizers; Phase noise; Synthesizers; Voltage-controlled oscillators; CMOS RF; Dual-Band; Frequency Synthesizer; Radio Transceivers; Wireless Communication;

fLanguage

English

Publisher

ieee

Conference_Titel

Radio Frequency Integrated Circuits Symposium, 2014 IEEE

Conference_Location

Tampa, FL

ISSN

1529-2517

Print_ISBN

978-1-4799-3862-9

Type

conf

DOI

10.1109/RFIC.2014.6851759

Filename

6851759