Probabilistic Error Model for Unreliable Nano-logic Gates

We propose a novel formalism, based on probabilistic Bayesian networks, to capture, analyze, and model dynamic errors at nano logic for probabilistic reliability analysis. It will be important for circuit designers to be able to compare and rank designs based on the expected output error, which is a measure of reliability. We propose an error model to estimate this expected output error probability, given the probability of these errors in each device. We estimate the overall output error probability by comparing the outputs of an ideal logic model with a dynamic error-encoded model. We use of Bayesian inference schemes for propagation of probabilities. Since exact inference is worst case NP-hard, we use two approximate inference schemes based on importance sampling, namely EPIS(Evidence Prepropagated Importance Sampling) and PLS (Probabilistic Logic Sampling), for handling mid-size benchmarks having up to 3500 gates. We demonstrate the efficiency and accuracy of these approximate inference schemes by comparing estimated results with logic simulation results.