Engineering Tunnel Barriers in Hybrid Silicon/Molecular Memory Devices

This paper discusses the role of asymmetric tunneling across oxide barriers in Hybrid Silicon/Molecular devices. Devices incorporating redox-active (ferrocene) molecules on silicon dioxide (SiO2) of varying thickness and Hafnium dioxide (HfO2)/SiO2stack on p-Si substrates were investigated as charge storage elements. The reduction (erase) process was found to be increasingly rate-limited as compared to oxidation (write) process with increasing SiO2thickness. This is attributed to asymmetric tunneling rates mainly due to a lower potential drop across the tunnel barrier for a given gate voltage during reduction process as compared to oxidation, resulting from higher surface potential drop in Si. Although increased SiO2thickness provides for improved retention, it severely retards write process. This can be overcome by employing asymmetric layered barrier of HfO2/SiO2which enhances effect of inherent asymmetric tunneling rates and also speeds up the write process due to higher relative permittivity and lower barrier offsets of HfO2/SiO2on Si as compared to SiO2. This behavior can be utilized to improve retention properties of these hybrid memory devices with minimal deterioration in write times.