Nanocomputing with Probabilistic Logic

This presentation considers the impact on logic design and computing of the fundamental unreliability of nanoscale device technologies. In general, these technologies will provide implementations of logic gates and circuits where logic levels are “0” or “1” with some probability related to the error rates of gates and interconnect. In this context, reliable circuit design becomes a problem of maximizing the probability of the correct logic levels of the output of the function implemented by the circuit for the relevant inputs. This presentation reviews some recent results and proposes new ideas for the characterization and design of probabilistic logic. Since the early days of computing it has been well known that the design of reliable arbitrary logic circuits is only possible if individual gates have error rates below some threshold which varies with gate functionality. Using bifurcation analysis of probabilistic gate models, thresholds for different types of gates are derived and their implications for logic design are revisited. Similar techniques are used to analyze multi-gate circuits and the functions they implement. The resulting thresholds provide reliability bounds for the circuits. Also considered are several proposed models for either analyzing reliability or maximizing it. Reference is also made to circuits designed to implement probabilistic computations.