DocumentCode :
1753382
Title :
An automated IP synthesizer for limited-resource DWT processor
Author :
Wei, Ting-Hsun ; Huang, Shiuh-Rong ; Dung, Lan-Rong
Author_Institution :
Department of Electrical and Control Engineering, National Chiao Tung University, Hsinchu, Taiwan, R.O.C.
Volume :
3
fYear :
2002
fDate :
13-17 May 2002
Abstract :
This paper presents a systematic design methodology for 1-D/2-D DWT processor based on a novel limited-resource scheduling algorithm. Given a set of architecture constraints and DWT parameters, the scheduling algorithm can generate four scheduling matrices that drive the data path to perform the DWT computation. Based on the limited-resource scheduling algorithm an automated DWT processor synthesizer has been developed and generates constrained DWT processors in the form of silicon intelligent property (SIP). The DWT SIP can be embedded into a SOC or mapped to program codes for commercial off-the-shelf (COTS) DSP processors with programmable devices. As a result, it has been successfully proven that a variety of DWT SIPs can be efficiently realized by tuning the parameters and applied for signal processing applications.
Keywords :
Computer architecture; Discrete wavelet transforms; Random access memory; Very large scale integration;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Acoustics, Speech, and Signal Processing (ICASSP), 2002 IEEE International Conference on
Conference_Location :
Orlando, FL, USA
ISSN :
1520-6149
Print_ISBN :
0-7803-7402-9
Type :
conf
DOI :
10.1109/ICASSP.2002.5745323
Filename :
5745323
Link To Document :
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