Title :
Extremely fast simulator for decoding LDPC codes
Author :
Yau, S.F. ; Wong, T.L. ; Lau, F.C.M.
Author_Institution :
Dept. of Electron. & Inf. Eng., Hong Kong Polytech. Univ., Hong Kong, China
Abstract :
Decoding low-density parity-check (LDPC) codes requires a lot of computation time, particularly when bit error rates as low as 10-9 are needed. In this paper, we improve the simulation speed by making use of an inexpensive graphics processing unit (GPU). A dedicated program is written to utilize the hardware resources in the GPU to decode LDPC codes in a parallel manner. Codes with rate 1/2 and length 2, 304 and 10, 008 are simulated by both GPU and central processing unit (CPU). We also show the average iteration time when LDPC codes with length 15, 000 and 20, 000 are simulated.
Keywords :
computer graphic equipment; coprocessors; decoding; parity check codes; CPU; GPU; LDPC code decoding; central processing unit; extreme fast simulator; graphics processing unit; low-density parity-check codes; Computational modeling; Decoding; Graphics processing unit; Instruction sets; Iterative decoding; Phase change materials; Fast decoding; GPU computing; LDPC codes;
Conference_Titel :
Advanced Communication Technology (ICACT), 2011 13th International Conference on
Conference_Location :
Seoul
Print_ISBN :
978-1-4244-8830-8