DVB-S2 LDPC finite-precision decoder

The latest standard of Digital Video Broadcasting (DVB-S2) features a powerful forward error correction system. This is enabled by replacing the concatenated Reed-Solomon/convolutional coding approach of DVB-S with a concatenation of an outer BCH code and inner low-density parity-check (LDPC) code, which is considered one of the most powerful codes known today and it can even outperform TurboCodes. In the decoding of LDPC code, huge data processing, storage, and interconnect requirements is a real challenge for decoder realization. For decoder hardware implementation, reduced complexity leads to low power consumption which might be a key implementation issue. This paper investigates the effect of the number of iteration and the decoder´s input quantization to achieve a significant improvement in the hardware implementation of the decoder architecture and hence leading to lower delay, higher throughput, reduction of area and power consumption in the whole radio receiver.