Advances on NiPt SALICIDE process optimization for 28nm CMOS manufacturing

Author

Chen, Vi-Wei ; Ho, Nien-Ting ; Lai, Jerander ; Lin, J.F. ; Huang, C.C. ; Wu, J.Y. ; Chu, James M M ; Butterbaugh, Jeffery W.

Author_Institution

UMC, Shinhih, Taiwan

fYear

2010

fDate

18-20 Oct. 2010

Firstpage

1

Lastpage

4

Abstract

A NiPt silicide for CMOS ohmic contact formation process extension from 45nm to 28nm node has been achieved through co-optimization of NiPt alloy deposition thickness, Pt additive amount and complementarty wet selective etch process. In this study, it was found thicker NiPt film will lead to lower sheet resistance (Rs)but will reach saturation; meanwhile, will increase NiSi encroachment. To increase Pt additive will significantly retard NiSi encroachment behavior, but also increase difficulty of wet selective etch process that followed. The co-optimization has achieved with linear programming of NiPt film, Pt additive and complemented by new wet etch processor.

Keywords

CMOS integrated circuits; MOSFET; additives; electrical resistivity; electron beam deposition; etching; linear programming; metallic thin films; nickel alloys; ohmic contacts; platinum alloys; semiconductor device manufacture; thin film transistors; CMOS manufacturing; NiPt; additive; alloy deposition thickness; complementarty wet selective etch process; linear programming; ohmic contact formation process; salicide process optimization; sheet resistance; size 45 nm to 28 nm; wet etch processor; Delta modulation;

fLanguage

English

Publisher

ieee

Conference_Titel

Semiconductor Manufacturing (ISSM), 2010 International Symposium on

Conference_Location

Tokyo

ISSN

1523-553X

Print_ISBN

978-1-4577-0392-8

Electronic_ISBN

1523-553X

Type

conf

Filename

5750248