DocumentCode :
1753981
Title :
Ultra Thin silicon substrate for next generation technology nodes
Author :
Schwarzenbach, W. ; Cauchy, X. ; Bonnin, O. ; Boedt, F. ; Butaud, E. ; Moulin, C. ; Kerdiles, S. ; Gilbert, J.-F. ; Daval, N. ; Aulnette, C. ; Girard, C. ; Oshimi, M.Y. ; Maleville, C.
Author_Institution :
SOITEC, Crolles, France
fYear :
2010
fDate :
18-20 Oct. 2010
Firstpage :
1
Lastpage :
3
Abstract :
Ultra Thin Body Devices are a way to solve technical challenges requested by advanced digital technology nodes. Combined with planar CMOS approach, they lead to the need for Ultra-Thin SOI (UTSOI) wafers. These 300 mm ultra-thin SOI layer are now available with silicon target thickness at 12 nm, controlled within a few angström range from Wafer to Wafer to Transistor level.Ultra-Thin SOI & BOX (UTBOX) substrates with 25 to 10 nm BOX are developed in parallel to UTSOI and will show similar SOI layer uniformity.
Keywords :
CMOS integrated circuits; silicon-on-insulator; UTSOI wafers; next generation technology nodes; planar CMOS approach; ultra thin body devices; ultra thin silicon substrate; ultra-thin SOI wafers; Lead; Substrates; Thickness measurement;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Semiconductor Manufacturing (ISSM), 2010 International Symposium on
Conference_Location :
Tokyo
ISSN :
1523-553X
Print_ISBN :
978-1-4577-0392-8
Electronic_ISBN :
1523-553X
Type :
conf
Filename :
5750250
Link To Document :
https://search.ricest.ac.ir/dl/search/defaultta.aspx?DTC=49&DC=1753981
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