DocumentCode :
1753987
Title :
Self-aligned critical line for LSI yield improvement
Author :
Sugimoto, Masaaki
Author_Institution :
Renesas Electron. Corp., Kawasaki, Japan
fYear :
2010
fDate :
18-20 Oct. 2010
Firstpage :
1
Lastpage :
4
Abstract :
This paper proposes a data management method which can characterize a process-stableness efficiently for an LSI yield improvement. Generally, a process capability of a wafer-processing improves day by day, though the yield suddenly degrades by some incidents. Thus, we define a tolerance for each measurement data in a conventional evaluation system, then, we must reduce each tolerance timely after the capability improving.
Keywords :
integrated circuit yield; large scale integration; LSI yield improvement; data management method; process capability; process stability; self-aligned critical line;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Semiconductor Manufacturing (ISSM), 2010 International Symposium on
Conference_Location :
Tokyo
ISSN :
1523-553X
Print_ISBN :
978-1-4577-0392-8
Electronic_ISBN :
1523-553X
Type :
conf
Filename :
5750256
Link To Document :
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