Reliability testing of high aspect ratio through silicon vias fabricated with atomic layer deposition barrier, seed layer and direct plating and material properties characterization of electrografted insulator, barrier and seed layer for 3-D integration

In this work the physical and electrical properties of metal-insulator-semiconductor devices using an electrografted insulator were characterized, including breakdown voltage, flat band capacitance and effective trap density and compared with reference thermal oxide layers. In addition, direct Cu plating on ALD barrier and seed layer into high aspect ratio TSVs was demonstrated and characterized. Thickness, roughness, and resistivity were characterized. Preliminary reliability testing on both processes was performed, showing good initial results with no major changes in film properties. These methods are attractive candidates for use in deposition of insulator, barrier and seedlayer into high aspect ratio TSVs for 3D integration applications.