Timing analysis and optimization for 3D stacked multi-core microprocessors

In this paper we demonstrate the methodology for designing and optimizing the LEON3 multi-core microprocessor in 3D stacked ICs. Based on GDSII-level details, we compare the 3D IC implementations as well as the traditional 2D IC implementation. For 3D IC implementation, we compare three partitioning styles: core-level, block-level, and gate-level. These partitioning styles represent three most relevant 3D implementation choices. The design methodology for such partitioning styles and their implications on the physical layout are discussed. Then we propose two methods to perform timing optimizations for 3D stacked ICs: timing scaling and timing budgeting. By analyzing the timing constraints from each method and the effects on the timing results and the layout, we show that each method has different impacts on the overall design quality. Lastly, we discuss additional 3D optimization opportunities.