Pixel detectors in 3D technologies for high energy physics

This paper reports on the current status of the development of International Linear Collider vertex detector pixel readout chips based on multi-tier vertically integrated electronics. Initial testing results of the VIP2a prototype are presented. The chip is the second embodiment of the prototype data-pushed readout concept developed at Fermilab. The device was fabricated in the MIT-LL 0.15 μm fully depleted SOI process. The prototype is a three-tier design, featuring 30×30 μm² pixels, laid out in an array of 48×48 pixels.