DocumentCode
1754217
Title
Automatic Memory Partitioning: Increasing memory parallelism via data structure partitioning
Author
Asher, Yosi Ben ; Rotem, Nadav
Author_Institution
Comput. Sci. Dept., Haifa Univ., Haifa, Israel
fYear
2010
fDate
24-29 Oct. 2010
Firstpage
155
Lastpage
161
Abstract
In high-level synthesis, pipelined designs are often restricted by the number of memory banks available to the synthesis system. Using multiple memory banks can improve the performance of accelerated applications. Currently, programmers must manually assign data structures to specific memory banks on the accelerator. This paper presents Automatic Memory Partitioning, a method for automatically partitioning data structures into multiple memory banks for increased parallelism and performance. We use source code instrumentation to collect memory traces in order to detect linear memory access patterns. The memory traces are used to split data structures into disjoint memory regions and determine which segments may benefit from parallel memory access. Experiments show significant improvements in performance while using a minimal number of memory banks.
Keywords
data structures; high level synthesis; logic partitioning; parallel memories; automatic memory partitioning; data structure partitioning; high level synthesis; memory parallelism; multiple memory bank; parallel memory access; Arrays; Color; Field programmable gate arrays; Hardware; Instruments; Resource management; FPGA; Memory; Parallelism;
fLanguage
English
Publisher
ieee
Conference_Titel
Hardware/Software Codesign and System Synthesis (CODES+ISSS), 2010 IEEE/ACM/IFIP International Conference on
Conference_Location
Scottsdale, AZ
Print_ISBN
978-1-6055-8905-3
Type
conf
Filename
5751495
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