• DocumentCode
    1754227
  • Title

    NeuroNoC: Neural network inspired runtime adaptation for an on-chip communication architecture

  • Author

    Ebi, Thomas ; Faruque, Mohammad Abdullah Al ; Henkel, Jörg

  • Author_Institution
    Dept. of Embedded Syst., Karlsruhe Inst. of Technol. (KIT), Karlsruhe, Germany
  • fYear
    2010
  • fDate
    24-29 Oct. 2010
  • Firstpage
    223
  • Lastpage
    230
  • Abstract
    The on-chip communication architecture presented in this paper, NeuroNoC, addresses the problems arising in large multi-core systems where global or local routing strategies do not work efficiently anymore since they either do not scale or lack information on the network state. Our communication architecture is runtime adaptive and it deploys a distributed artificial neural network to aid routing decisions. It thereby provides a light-weight mechanism for local routing information to propagate through the communication architecture and is capable of self-organizing efficiently (since scalable) to varying communication workload scenarios. The underlying basic concepts are borrowed from spiking neural networks, a special case of artificial neural networks. Our experiments show that already with low hardware overhead, a significant improvement of the runtime routing behavior compared to current state-of-the-art approaches is possible. We report an improvement of 23% in routing quality compared to wXY routing in terms of failed transactions.
  • Keywords
    multiprocessing systems; multiprocessor interconnection networks; network-on-chip; neural nets; NeuroNoC; communication workload scenario; distributed artificial neural networks; local routing information; multicore system; neural network inspired runtime adaptation; onchip communication architecture; routing decision; spiking neural networks; Artificial neural networks; Bandwidth; Biomembranes; Computer architecture; Kernel; Neurons; Routing; Adaptive system; Network-on-Chip; Spiking Neural Networks;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Hardware/Software Codesign and System Synthesis (CODES+ISSS), 2010 IEEE/ACM/IFIP International Conference on
  • Conference_Location
    Scottsdale, AZ
  • Print_ISBN
    978-1-6055-8905-3
  • Type

    conf

  • Filename
    5751505