• DocumentCode
    1754243
  • Title

    Rank based dynamic voltage and frequency scaling for tiled graphics processors

  • Author

    Silpa, B.V.N. ; Krishnaiah, Gummidipudi ; Panda, Preeti Ranjan

  • Author_Institution
    Dept. of CSE, IIT Delhi, New Delhi, India
  • fYear
    2010
  • fDate
    24-29 Oct. 2010
  • Firstpage
    3
  • Lastpage
    12
  • Abstract
    With increasing interest in sophisticated graphics capabilities in mobile systems, energy consumption of graphics hardware is becoming a major design concern in addition to the traditional performance enhancement criteria. Our study of various modern games substantiates the observation that the workload of games varies significantly with time and hence can benefit from dynamic voltage and frequency scaling (DVFS). Since visual quality of graphics applications is highly dependent on the rate at which frames are processed, it is important to devise a DVFS scheme that minimizes deadline misses due to inaccuracies in workload prediction. In this paper, we demonstrate that tiled-graphics renderers exhibit substantial advantages over immediate-mode renderers in obtaining access to frame parameters that help in enhancing the workload estimation accuracy. We also show that, operating at a finer granularity of “tiles” as opposed to “frames” allows early detection and corrective action in case of a mis-prediction. We propose an accurate workload estimation technique and two DVFS schemes: (i) tile-history based DVFS and (ii) tile-rank based DVFS for tiled-rendering architectures. The proposed schemes are demonstrated to be more efficient in terms of power and performance than the frame level DVFS schemes proposed in recent literature. With a system with 8 DVFS levels, our tile-history based DVFS scheme results in 60% improvement in quality (deadline misses) over the frame history based DVFS schemes and gives 58% saving in energy. The more sophisticated tile-rank based scheme achieves 75% improvement in quality over the frame history based DVFS scheme and results in 58% saving in energy. We have also compared the efficiency of the proposed tile-level DVFS schemes with frame-level schemes for different number of DVFS levels, and found that while the frame-level schemes suffer from increasing deadline misses as the frequency levels increase, the im pact on tile-level schemes is negligible. The Energy per Frame-rate for our scheme is the minimum, indicating that it delivers the best performance-energy results.
  • Keywords
    computer graphic equipment; coprocessors; power aware computing; rendering (computer graphics); DVFS schemes; energy per frame-rate; rank based dynamic frequency scaling; rank based dynamic voltage scaling; tile-history based DVFS; tile-rank based DVFS; tiled graphics processors; tiled-rendering architectures; workload estimation technique; workload prediction; Computer architecture; Equations; Graphics; Graphics processing unit; Lead; Dynamic Voltage and Frequency Scaling; Graphics Processor; Low Power; Workload Prediction;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Hardware/Software Codesign and System Synthesis (CODES+ISSS), 2010 IEEE/ACM/IFIP International Conference on
  • Conference_Location
    Scottsdale, AZ
  • Print_ISBN
    978-1-6055-8905-3
  • Type

    conf

  • Filename
    5751521