• DocumentCode
    1754441
  • Title

    Reconfigured-Wafer-to-Wafer 3-D Integration Using Parallel Self-Assembly of Chips With Cu–SnAg Microbumps and a Nonconductive Film

  • Author

    Fukushima, Tetsuya ; Bea, Jichel ; Kino, Hitoshi ; Nagai, C. ; Murugesan, Mariappan ; Hashiguchi, Hironori ; Kang-Wook Lee ; Tanaka, T. ; Koyanagi, Mitsumasa

  • Author_Institution
    New Ind. Creation Hatchery Center, Tohoku Univ., Sendai, Japan
  • Volume
    61
  • Issue
    2
  • fYear
    2014
  • fDate
    Feb. 2014
  • Firstpage
    533
  • Lastpage
    539
  • Abstract
    A new 3-D integration concept based on reconfigured wafer-to-wafer stacking is proposed. Using reconfigured wafer-to-wafer 3-D integration, many known-good dies (KGDs) can be simultaneously and precisely self-assembled by water surface tension onto a carrier wafer, which is called a reconfigured wafer. In addition, the KGDs on the reconfigured wafer can be transferred and bonded to another target wafer at the wafer level. The alignment accuracy is within 1 μm when 3 × 3-, 5 × 5-, 4 × 9,- or 10 × 10- mm2 chips are employed. To 3-D stack many KGDs in a batch process, we developed and employed a self-assembly multichip bonder. KGDs with 20- μm-pitch Cu-SnAg microbumps covered with a nonconductive film as a preapplied underfill material on their top surface were self-assembled right-side up, and then transferred to the corresponding target interposer wafer upside down. The resulting daisy chain with 500 Cu-SnAg microbumps exhibited ohmic contacts, and the resistance of ~ 40 mΩ/bump was sufficiently low for 3-D large-scale integration application.
  • Keywords
    copper; microassembling; ohmic contacts; self-assembly; silver alloys; surface tension; thin films; three-dimensional integrated circuits; tin alloys; wafer bonding; wafer-scale integration; Cu-SnAg; KGD; carrier wafer; daisy chain; known-good dies; microbump; multichip bonding; nonconductive film; ohmic contact; parallel chip self-assembly; preapplied underfill material; reconfigured-wafer-to-wafer 3D integration; size 1 mum; wafer bonding; wafer-to-wafer stacking; water surface tension; Accuracy; Assembly; Bonding; Liquids; Self-assembly; Stacking; Wiring; 3-D integration; alignment; microbump; self-assembly; wafer-level processing; water surface tension;
  • fLanguage
    English
  • Journal_Title
    Electron Devices, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0018-9383
  • Type

    jour

  • DOI
    10.1109/TED.2013.2294831
  • Filename
    6698357