Integrated Algorithm for 3-D IC Through-Silicon Via Assignment

Through-silicon via (TSV) with flip-chip packaging is a technology that enables vertical integration of silicon dies, forming a single 3-D IC stack. A practical model for preplaced TSV assignment of 3-D nets is proposed for this technology. We prove that the general preplaced 3-D IC TSV assignment problem with more than two dies is NP-complete. An integrated algorithm that combines shortest path search, bipartite matching, min-cost max-flow calculation, and postprocessing is developed. Experimental results using actual testing silicon data demonstrate that our flow achieves good results with reasonable runtime when compared to other existing works.