DocumentCode
1755012
Title
Eleven Ways to Boost Your Synchronizer
Author
Beer, Salomon ; Ginosar, Ran
Author_Institution
Dept. of Electr. Eng., Technion - Israel Inst. of Technol., Haifa, Israel
Volume
23
Issue
6
fYear
2015
fDate
42156
Firstpage
1040
Lastpage
1049
Abstract
Synchronizers play an essential role in multiple clock domain systems-on-chip. The most common synchronizer consists of a series of pipelined flip-flops. Several factors influence the performance of synchronizers: circuit design, process technology, and operating conditions. Global factors apply to the entire integrated circuit, while others can be adjusted for each individual synchronizer in the design. The following guidelines are provided to improve synchronizers: avoiding scan and reset, selecting minimum size flip-flop cells, minimizing routing, reducing jitter in coherent clock domain crossings, opting for high-performance process flavor and minimumVTH, overprovisioning to account for variations, maximizing supply voltage, and manipulating clock duty cycle.
Keywords
clocks; flip-flops; logic design; synchronisation; system-on-chip; circuit design; clock duty cycle manipulation; coherent clock domain crossing; flip-flop cell selection; global factors; jitter reduction; multiple clock domain systems-on-chip; operating conditions; overprovisioning method; process technology; reset avoidance; routing minimization; scan avoidance; supply voltage maximization; synchronizer boosting; threshold voltage minimization; Capacitance; Clocks; Latches; Libraries; Logic gates; Synchronization; Transistors; MTBF; Metastability; multistage synchronizers; synchronization; synchronizer; tau effective; tau effective.;
fLanguage
English
Journal_Title
Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
Publisher
ieee
ISSN
1063-8210
Type
jour
DOI
10.1109/TVLSI.2014.2331331
Filename
6851932
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