Improved inverter-based read-out scheme for low-power ISFET sensing array

The digital read-out scheme in an ion-sensitive field effect transistor (ISFET) sensing array is more advantageous when compared with the analogue counterpart because of its lower power consumption, smaller area and less susceptibility to environmental noise and parasitics. An improved read-out scheme is proposed in which each ISFET is stacked with a CMOS inverter to form a pH-to-time converter. The pH level of the solution regulates the strength of the ISFET, which in turn modulates the delay of the stacked inverter and hence the pulse width of the output signal. Simulation results using the 0.18 μm/2.5 V CMOS process show that the modulated pulse width changes linearly over a wide range of pH. The design achieves five orders of magnitude smaller leakage and 40% lower dynamic power consumption, while it requires only 50% of silicon area when compared with the conventional design. It is therefore more suitable for large ISFET arrays implemented in nano-scale CMOS technologies.