DocumentCode
17553
Title
Stack Gate Technique for Dopingless Bulk FinFETs
Author
Yi-Bo Liao ; Meng-Hsueh Chiang ; Yu-Sheng Lai ; Wei-Chou Hsu
Author_Institution
Dept. of Electr. Eng., Nat. Cheng Kung Univ., Tainan, Taiwan
Volume
61
Issue
4
fYear
2014
fDate
Apr-14
Firstpage
963
Lastpage
968
Abstract
FinFETs have been made successfully for mass manufacturing on bulk and silicon-on-insulator wafers. When choosing the bulk option, additional process steps are needed for substrate leakage suppression. Typically, heavy substrate doping for punchthrough stopping between the source and drain is used, but precise control of the doping profile to prevent its up-diffusion into the channel has been a challenging task, especially for continuously shrinking device dimension. In this paper, we propose a stack gate structure with doping-free substrate while punchthrough leakage can be suppressed. The proposed technique can be integrated in conventional gate-last high-k metal gate process. Both polysilicon and metal gates are shown to be feasible in the proposed stack gate based on 3-D TCAD simulation. In addition, the stack gate structure without substrate doping is immune to its random dopant fluctuations.
Keywords
MOSFET; high-k dielectric thin films; silicon-on-insulator; 3D TCAD simulation; Si; bulk wafer; continuously-shrinking device dimension; doping profile; doping-free substrate; dopingless bulk FinFET; gate-last high-k metal gate process; heavy substrate doping; mass manufacturing; metal gate; polysilicon gate; punchthrough leakage suppression; punchthrough stopping; random dopant fluctuation; silicon-on-insulator wafer; stack gate structure; stack gate technique; substrate leakage suppression; up-diffusion prevention; Doping; FinFETs; Leakage currents; Logic gates; Metals; Semiconductor process modeling; Substrates; Bulk FinFET; stack gate; substrate doping;
fLanguage
English
Journal_Title
Electron Devices, IEEE Transactions on
Publisher
ieee
ISSN
0018-9383
Type
jour
DOI
10.1109/TED.2014.2306012
Filename
6755551
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