Design Methodology for Optical Interconnect Topologies in NoCs With BER and Transmit Power Constraints

Optical Network-on-Chip (ONoC) has emerged as an enabling technology to integrate a large number of processing cores in a single die. In this paper, we review some of the existing optical interconnect topologies for ONoCs and, propose a novel optical topology using multiple-segment buses (MSB) wherein several clusters of cores are interconnected in optical domain using MSB-based multiple optical interconnects. In particular, we analyze the bit-error rate (BER) performance of various ONoC topologies including the proposed MSB topology, taking into account signal losses and crosstalk components along the signal paths. The proposed MSB topology for 16 clusters offers an encouraging BER performance as compared to the other existing topologies, within the acceptable limit of per-wavelength launched power (1.5 mW). The BER performance in 16-cluster MSB topology is further improved by incorporating forward error-correcting codes in the communicating clusters. Having studied the 16-cluster MSB topology, the size of the ONoC is scaled up to 64 clusters, wherein the 16-cluster topologies are used as modular MSB units (MUs), which are interconnected by inter-MU buses with optical-electronic-optical conversions at the exit and entry points from and into the communicating MUs. For 64-cluster modular MSB, the impacts of error-correcting codes are also examined. Finally, the paper provides a study on the impact of thermal mistuning of MRRs on the average BER of ONoCs, leading to a requirement of 20 MHz laser linewidth to achieve an extinction ratio of 15 dB for the ONoC setting considered in the study.