Title :
Wafer-Level Packaging Design With Through Substrate Grooves as Interconnection for GaAs-Based Image Sensor
Author :
Shuangfu Wang ; Jiaotuo Ye ; Gaowei Xu ; Le Luo
Author_Institution :
State Key Lab. of Transducer Technol., Shanghai Inst. of Microsyst. & Inf. Technol., Shanghai, China
Abstract :
A wafer-level packaging design for GaAs-based image sensor is presented. Key processes, such as GaAs/glass wafer bonding, GaAs substrate thinning, through substrate grooves (TSGs) fabrication, redistribution layer formation, polymer passivation, and laser jet bumping, are examined and characterized. GaAs image sensor package with 64 leads is successfully fabricated on 4-in thinned GaAs/glass test vehicle wafer. In the package, two long TSGs are wet etched as the interconnection path. Process parameters are systematically studied and given. Then, fabrication results of these processes were discussed. Finally, electrical tests show that ohmic contact is obtained with a resistance of around 30 Ω between two nearby interconnections.
Keywords :
III-V semiconductors; etching; gallium arsenide; image sensors; integrated circuit design; integrated circuit interconnections; integrated circuit testing; passivation; polymers; substrates; wafer bonding; wafer level packaging; GaAs; TSG fabrication; electrical tests; glass test vehicle wafer; glass wafer bonding; image sensor package; interconnection path; laser jet bumping; ohmic contact; polymer passivation; process parameters; redistribution layer formation; substrate thinning; through substrate grooves; wafer-level packaging design; wet etching; CMOS image sensors; Charge coupled devices; Gallium arsenide; Wafer bonding; Wafer scale integration; Wet etching; GaAs image sensor; process; through substrate grooves (TSGs); wafer-level packaging;
Journal_Title :
Components, Packaging and Manufacturing Technology, IEEE Transactions on
DOI :
10.1109/TCPMT.2013.2277607
