DocumentCode
1755541
Title
Tiny - optimised 3D mesh NoC for area and latency minimisation
Author
Marcon, Cesar ; Webber, Thais ; Fernandes, R. ; Cataldo, Robert ; Grando, Fernando ; Poehls, L. ; Benso, Alfredo
Author_Institution
Ipiranga, PUCRS Univ., Porto Alegre, Brazil
Volume
50
Issue
3
fYear
2014
fDate
January 30 2014
Firstpage
165
Lastpage
166
Abstract
Tiny is a scalable and efficient three-dimensional (3D) network-on-chip (NoC) designed to reduce latency and area. A theoretical analysis demonstrates its efficiency when compared with a basic 3D mesh NoC. Mapping independent traffics with different injection rates makes the trade-offs analysis of Tiny possible. Results highlight that Tiny always reduces area and for several cases minimises latency.
Keywords
integrated circuit design; network-on-chip; Tiny-optimised 3D mesh NoC; area reduction; basic 3D mesh NoC; efficient three-dimensional network-on-chip design; injection rates; latency minimisation; scalable 3D NoC design; theoretical analysis; traffic mapping;
fLanguage
English
Journal_Title
Electronics Letters
Publisher
iet
ISSN
0013-5194
Type
jour
DOI
10.1049/el.2013.2557
Filename
6731740
Link To Document