• DocumentCode
    1756917
  • Title

    Circuit-Level Simulation of a CNTFET With Unevenly Positioned CNTs by Linear Programming

  • Author

    Geunho Cho ; Lombardi, Floriana

  • Author_Institution
    Dept. of Electr. & Comput. Eng., Northeastern Univ., Boston, MA, USA
  • Volume
    14
  • Issue
    1
  • fYear
    2014
  • fDate
    41699
  • Firstpage
    234
  • Lastpage
    244
  • Abstract
    The carbon nanotube field-effect transistor (CNTFET) has been advocated as one of the possible alternatives to replace the MOSFET. Some of the likely defect types that may occur in its manufacturing process are the presence of undeposited CNTs and the change in CNT diameter. Existing simulation models are inadequate to assess the effect of undeposited CNTs, due to the limitation in representing these CNT defects for circuit-level simulation and the high execution complexity. In this paper, a new method to evaluate CNTFETs with uneven spacing between CNTs (such as due to undeposited CNTs as defects) for circuit-level simulation is proposed; it is based on an equivalence relationship in some key performance metrics (current and gate capacitance) between CNTFETs with evenly/unevenly positioned CNTs. This relationship requires the adjustment of different parameters of the CNTFET. Using existing CNTFET models (based on MATLAB and HSPICE), linear programming is utilized to find the values of the relevant parameters (number, pitch, doping level, and chirality) of the simulation tools. The equivalence relationship is then established for circuit-level simulation. Different performance metrics (delay and energy) are presented for a five-stage fan-out-of-four inverter chain, under the conditions of evenly and unevenly positioned CNTs in the CNTFET. Computational requirements (such as simulation time and memory usage) of the proposed approach are reported; it is shown that the equivalence relation by adjusting the required parameters and the circuit-level evaluation of the CNTFET is computationally possible at a modest error (6% on average).
  • Keywords
    carbon nanotube field effect transistors; chirality; linear programming; semiconductor device models; semiconductor doping; CNT chirality; CNT defect; CNTFET; carbon nanotube field effect transistor; circuit level simulation; doping level; inverter chain; key performance metrics; linear programming; undeposited CNT; unevenly positioned CNT; CNTFETs; Capacitance; Doping; Integrated circuit modeling; Linear programming; Logic gates; MATLAB; CNT; CNTFET; defect model; emerging technologies; manufacturing; simulation;
  • fLanguage
    English
  • Journal_Title
    Device and Materials Reliability, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    1530-4388
  • Type

    jour

  • DOI
    10.1109/TDMR.2013.2279154
  • Filename
    6583982