• DocumentCode
    1757183
  • Title

    Device-Circuit Co-Optimization for Robust Design of FinFET-Based SRAMs

  • Author

    Gupta, Sumeet Kumar ; Roy, Kaushik

  • Author_Institution
    Sch. of Electr. & Comput. Eng., Purdue Univ., West Lafayette, IN, USA
  • Volume
    30
  • Issue
    6
  • fYear
    2013
  • fDate
    Dec. 2013
  • Firstpage
    29
  • Lastpage
    39
  • Abstract
    A set of device-circuit co-design techniques oriented to increase the resilience of FinFET SRAMs circuits is presented in this paper. Co-optimization of fin ratio, thickness, orientation and height are investigated and its impact on performance and area evaluated.
  • Keywords
    MOS memory circuits; SRAM chips; circuit optimisation; logic design; FinFET SRAM circuit; device circuit co-design technique; device circuit co-optimization; Aging; Circuit stability; Equipment; FinFETs; Logic gates; Optimization; Random access memory; Stability analysis; Co-design; FinFET; Process Variations; SRAM;
  • fLanguage
    English
  • Journal_Title
    Design & Test, IEEE
  • Publisher
    ieee
  • ISSN
    2168-2356
  • Type

    jour

  • DOI
    10.1109/MDAT.2013.2266394
  • Filename
    6525400
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1757183