Title :
A 100-Channel 1-mW Implantable Neural Recording IC
Author :
Xiaodan Zou ; Lei Liu ; Jia Hao Cheong ; Lei Yao ; Peng Li ; Ming-Yuan Cheng ; Wang Ling Goh ; Rajkumar, R. ; Dawe, Gavin Stewart ; Kuang-Wei Cheng ; Minkyu Je
Author_Institution :
Inst. of Microelectron., A*STAR (Agency for Sci., Technol. & Res.), Singapore, Singapore
Abstract :
This paper presents a fully implantable 100-channel neural interface IC for neural activity monitoring. It contains 100-channel analog recording front-ends, 10 multiplexing successive approximation register ADCs, digital control modules and power management circuits. A dual sample-and-hold architecture is proposed, which extends the sampling time of the ADC and reduces the average power per channel by more than 50% compared to the conventional multiplexing neural recording system. A neural amplifier (NA) with current-reuse technique and weak inversion operation is demonstrated, consuming 800 nA under 1-V supply while achieving an input-referred noise of 4.0 μVrms in a 8-kHz bandwidth and a NEF of 1.9 for the whole analog recording chain. The measured frequency response of the analog front-end has a high-pass cutoff frequency from sub-1 Hz to 248 Hz and a low-pass cutoff frequency from 432 Hz to 5.1 kHz, which can be configured to record neural spikes and local field potentials simultaneously or separately. The whole system was fabricated in a 0.18-μm standard CMOS process and operates under 1 V for analog blocks and ADC, and 1.8 V for digital modules. The number of active recording channels is programmable and the digital output data rate changes accordingly, leading to high system power efficiency. The overall 100-channel interface IC consumes 1.16-mW total power, making it the optimum solution for multi-channel neural recording systems.
Keywords :
CMOS integrated circuits; amplifiers; bioelectric potentials; biomedical electronics; frequency response; neurophysiology; sample and hold circuits; ADC; CMOS process; active recording channels; analog recording front-ends; current 800 nA; current-reuse technique; digital control modules; digital modules; frequency response; implantable neural recording; multiplexing successive approximation register; neural activity monitoring; neural amplifier; neural interface integrated circuit; power 1.16 mW; power management circuits; sample-and-hold architecture; size 0.18 mum; voltage 1 V; voltage 1.8 V; Band pass filters; Bandwidth; Cutoff frequency; Educational institutions; Noise; Power demand; Biomedical application; NEF; SAR ADC; capacitor-less LDO; current reuse; dual S/H; high power efficiency; low-noise neural amplifier; multi-channel neural recording system; power and area trade-off;
Journal_Title :
Circuits and Systems I: Regular Papers, IEEE Transactions on
DOI :
10.1109/TCSI.2013.2249175