High-Performance and Robust SRAM Cell Based on Asymmetric Dual-K Spacer FinFETs

This paper proposes a new asymmetric underlap Fin-Field Effect Transistor (FinFET) structure using a dual- k spacer. Asymmetric dual-spacer at source shows excellent gate control over the channel due to increase in the outer fringe field at gate/source underlap. Hence, this structure exhibits a superior short-channel effect metric over the conventional/single-spacer underlap FinFET. The proposed asymmetric structure enhances static random access memories (SRAMs) performance in terms of robustness, access times as well as leakage power during the hold, read, and write operations. The hold static noise margin and write margin increases by 5.16% and 5.66%, respectively. The read stability enhances by 13.75% and 19.35% over conventional FinFET SRAM circuit. Furthermore, the leakage power reduces by 60%, and write access time improves by 23.63%. Compared with conventional FinFET-based SRAM, same bit-cell area and read delay are associated with the proposed structure. Supply voltage scalability on SRAM design metrics is also investigated. In addition to SRAM application, underlap length, lateral source/drain doping gradient, and the high- k spacer width are optimized for high-performance digital applications.