Dual-Scan Parallel Flipping Architecture for a Lifting-Based 2-D Discrete Wavelet Transform

In this brief, an efficient dual-scan parallel flipping architecture for a lifting-based 2-D discrete wavelet transform is presented. This proposed novel algorithm is based on a flipping technique to implement a modular and hardware-efficient architecture with a very simple control path. In the proposed algorithm, the serial operation of the lifting data flow is optimized using parallel computations of independent paths in advance with pipeline operation to minimize the critical path to one multiplier delay and to achieve 100% hardware utilization efficiency. The proposed architecture is repeatable and only uses five transposition registers. The architecture can be folded to reduce the data path to only six multipliers and eight adders without affecting the critical path. The architecture implemented on a field-programmable gate-array target indicates better hardware efficiency.