DocumentCode
1758497
Title
Litho Machine Scheduling With Convex Hull Analyses
Author
Bing Yan ; Hsin Yuan Chen ; Luh, Peter B. ; Wang, Shuhui ; Chang, Joana
Author_Institution
Dept. of Electr. & Comput. Eng., Univ. of Connecticut, Storrs, CT, USA
Volume
10
Issue
4
fYear
2013
fDate
Oct. 2013
Firstpage
928
Lastpage
937
Abstract
The increasing pressure to meet demand are forcing semiconductor manufacturers to seek efficient scheduling methods. Lithography, with a limited number of expensive resources and the reentrant nature of the fabrication processes, is a major bottleneck. This paper presents a litho machine scheduling formulation for high-volume and low-variety manufacturing over a day, with novel modeling of resource setups, reticle expirations, and future stacking layer load balancing. The problem is believed to be NP hard. After linearization and simplification, it is solved by using the branch-and-cut method by exploiting problem linearity. Near-optimal solutions for practical problems, however, are still difficult to obtain efficiently. Through detailed analyses, it was discovered that the convex hull of the problem is difficult to delineate and many low-efficient branching operations are needed. A two-phase approach is therefore established. In the first phase, a simplified problem with certain complicating constraints dropped is efficiently solved by exploiting linearity to reduce ranges of decision variables. The problem with the full set of constraints is then solved in the second phase with a much reduced decision space. Numerical testing shows that this two-phase approach can generate near-optimal schedules within reasonable amounts of computation time. This two-phase approach is generic, and will have major implications on other semiconductor scheduling problems and beyond.
Keywords
lithography; optimisation; scheduling; semiconductor device manufacture; tree searching; NP hard problem; branch-and-cut method; branching operations; convex hull analyses; fabrication; linearization; lithography machine scheduling; resource setup modeling; semiconductor manufacturers; stacking layer load balancing; Job shop scheduling; Linear programming; Lithography; Load modeling; Processor scheduling; Semiconductor device manufacture; Stacking; Branch-and-cut; convex hull; litho machine scheduling; mixed-integer optimization; semiconductor manufacturing; two-phase approach;
fLanguage
English
Journal_Title
Automation Science and Engineering, IEEE Transactions on
Publisher
ieee
ISSN
1545-5955
Type
jour
DOI
10.1109/TASE.2013.2277812
Filename
6584819
Link To Document