• DocumentCode
    1758741
  • Title

    Low-Power Programmable PRPG With Test Compression Capabilities

  • Author

    Filipek, Michal ; Mrugalski, Grzegorz ; Mukherjee, Nilanjan ; Nadeau-Dostie, Benoit ; Rajski, Janusz ; Solecki, Jedrzej ; Tyszer, Jerzy

  • Author_Institution
    Fac. of Electron. & Telecommun., Poznan Univ. of Technol., Poznan, Poland
  • Volume
    23
  • Issue
    6
  • fYear
    2015
  • fDate
    42156
  • Firstpage
    1063
  • Lastpage
    1076
  • Abstract
    This paper describes a low-power (LP) programmable generator capable of producing pseudorandom test patterns with desired toggling levels and enhanced fault coverage gradient compared with the best-to-date built-in self-test (BIST)-based pseudorandom test pattern generators. It is comprised of a linear finite state machine (a linear feedback shift register or a ring generator) driving an appropriate phase shifter, and it comes with a number of features allowing this device to produce binary sequences with preselected toggling (PRESTO) activity. We introduce a method to automatically select several controls of the generator offering easy and precise tuning. The same technique is subsequently employed to deterministically guide the generator toward test sequences with improved fault-coverage-to-pattern-count ratios. Furthermore, this paper proposes an LP test compression method that allows shaping the test power envelope in a fully predictable, accurate, and flexible fashion by adapting the PRESTO-based logic BIST (LBIST) infrastructure. The proposed hybrid scheme efficiently combines test compression with LBIST, where both techniques can work synergistically to deliver high quality tests. Experimental results obtained for industrial designs illustrate the feasibility of the proposed test schemes and are reported herein.
  • Keywords
    automatic test pattern generation; built-in self test; finite state machines; logic testing; low-power electronics; PRESTO activity; built-in self-test; enhanced fault coverage gradient; linear finite state machine; logic BIST infrastructure; low power programmable PRPG; phase shifter; preselected toggling; producing pseudorandom test pattern; programmable generator; test compression capabilities; Built-in self-test; Generators; Latches; Logic gates; Phase shifters; Registers; Switches; Built-in self-test (BIST); low-power (LP) test; pseudorandom test pattern generators (PRPGs); test data volume compression; test data volume compression.;
  • fLanguage
    English
  • Journal_Title
    Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    1063-8210
  • Type

    jour

  • DOI
    10.1109/TVLSI.2014.2332465
  • Filename
    6855371