Fast hardware architecture for grey-level image morphology with flat structuring elements

Mathematical morphology operators, applied in many vision-based applications, are characterised by repetitive operations on large amounts of data. Thus, novel design strategies for efficient hardware implementations are necessary. This study presents and evaluates a real-time hardware architecture for grey-level image erosion and dilation that processes data in streams for an efficient utilisation of memory bandwidth and low on-chip memory requirements. A low-complexity and highly modular architecture is proposed based on a sequence of pipeline stages, and parallel processing in order to minimise computational times. The design is intended to be used as a hardware accelerator in real-time embedded image processing applications requiring moderate-size and non-rectangular flat structuring elements on high-resolution images. The architecture is prototyped on a field programmable gate array device operating at a clock frequency of 260 MHz on a Virtex-6 device which compares favourably to the well-known delay-line-based hardware architectures in terms of complexity, memory requirements and execution time. A 7 × 7 dilation/erosion operator on 1280 × 1024 grey-level image can be performed at a rate of 95 frames per second, but the architecture can be scaled up if required.