• DocumentCode
    1759554
  • Title

    Protein Alignment Systolic Array Throughput Optimization

  • Author

    Causapruno, Giovanni ; Urgese, Gianvito ; Vacca, Marco ; Graziano, Mariagrazia ; Zamboni, Maurizio

  • Author_Institution
    Dept. of Electron. & Telecommun., Politec. di Torino, Turin, Italy
  • Volume
    23
  • Issue
    1
  • fYear
    2015
  • fDate
    Jan. 2015
  • Firstpage
    68
  • Lastpage
    77
  • Abstract
    Protein comparison is gaining importance year after year since it has been demonstrated that biologists can find correlation between different species, or genetic mutations that can lead to cancer and genetic diseases. Protein sequence alignment is the most computational intensive task when performing protein comparison. To speed-up alignment, dedicated processors that can perform different computations in parallel have been designed. Among them, the best performance has been achieved using systolic arrays (SAs). However, when the processing elements of the SA have an internal loop, performance could be highly reduced. In this paper, we present an architectural strategy to address this problem applying pipeline interleaving; this strategy is applied to an SA for Smith Waterman algorithm that we designed. Results encourage the adoption of pipeline interleaving for parallel circuits with loop-based processing elements. We demonstrate that important benefits in terms of higher operating frequency can be derived without so relevant costs as increased complexity, area, and power required.
  • Keywords
    genetics; lab-on-a-chip; optimisation; proteins; proteomics; systolic arrays; Smith Waterman algorithm; genetic mutations; loop-based processing elements; parallel circuits; pipeline interleaving; protein alignment systolic array throughput optimization; protein sequence alignment; Arrays; Delays; Heuristic algorithms; Matrices; Proteins; Registers; Throughput; CMOS; Smith-Waterman (S-W); interleaving; protein alignment; systolic arrays (SAs); systolic arrays (SAs).;
  • fLanguage
    English
  • Journal_Title
    Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    1063-8210
  • Type

    jour

  • DOI
    10.1109/TVLSI.2014.2302015
  • Filename
    6734689