Electrical Characterization of GaP-Silicon Interface for Memory and Transistor Applications

Author

Pal, Arnab ; Nainani, Aneesh ; Zhiyuan Ye ; Xinyu Bao ; Sanchez, E. ; Saraswat, Krishna C.

Author_Institution

Dept. of Electr. Eng., Stanford Univ., Stanford, CA, USA

Volume

60

Issue

7

fYear

2013

fDate

41456

Firstpage

2238

Lastpage

2245

Abstract

Process conditions of gallium phosphide (GaP) metal-organic chemical vapor deposition growth on silicon (Si) are optimized by material characterization. Thorough investigation of GaP-Si interface at this optimized growth condition is carried out by electrical characterization with the perspective of applying this heterostructure system for improving the performance of logic transistors and retention time of capacitorless single-transistor dynamic RAM (1T-DRAM). Fabricated GaP-Si heterojunction diodes exhibit an ON-OFF ratio of 10⁸ with similar reverse current as the ideal device simulation results signify immunity to the existing antiphase domains. Finally, MOSFET devices with GaP source-drain having subthreshold swing of 70 mV/dec and an ON-OFF ratio of 10⁵ are demonstrated.

Keywords

DRAM chips; III-V semiconductors; MOSFET; chemical vapour deposition; elemental semiconductors; gallium compounds; semiconductor diodes; silicon; 1T-DRAM; GaP source-drain; GaP-Si; GaP-Si heterojunction diodes; GaP-silicon interface; MOSFET devices; capacitorless single-transistor dynamic RAM; electrical characterization; gallium phosphide; heterostructure system; logic transistors; memory applications; metal-organic chemical vapor deposition growth; transistor applications; Antiphase domain and boundary; ON-and OFF-current; heterojunction diode; metal–organic chemical vapor deposition (MOCVD); x-ray diffraction;

fLanguage

English

Journal_Title

Electron Devices, IEEE Transactions on

Publisher

ieee

ISSN

0018-9383

Type

jour

DOI

10.1109/TED.2013.2264495

Filename

6527356