DocumentCode :
1759701
Title :
Finite Element Model of a Superconducting Fault Current Limiter Calibrated by Hardware-in-the-Loop Measurements
Author :
Graber, Lukas ; Chiocchio, T. ; Kvitkovic, Jozef ; Pamidi, Sastry ; Steurer, Michael ; Usoskin, Alexander
Author_Institution :
Center for Adv. Power Syst., Florida State Univ., Tallahassee, FL, USA
Volume :
24
Issue :
3
fYear :
2014
fDate :
41791
Firstpage :
1
Lastpage :
5
Abstract :
A bench top model of an inductive superconducting fault current limiter (iSFCL) has been designed based on wide tape of second generation high temperature superconducting (2GHTS) coated conductor. The tape forms a ring shielding a reduced size ferromagnetic core. The design was optimized using a finite element model, which was calibrated and refined by impedance measurements and power hardware-in-the-loop testing of the bench top iSFCL. The finite-element model was coupled with a lumped element circuit model that simulates the electric power grid. Usefulness of such coupled models for design optimization studies and for reduction of uncertainty in transient simulation models is demonstrated.
Keywords :
calibration; coatings; conductors (electric); electric impedance measurement; electronic engineering computing; ferromagnetic materials; finite element analysis; high-temperature superconductors; magnetic cores; magnetic shielding; superconducting fault current limiters; 2GHTS coated conductor; calibration; electric power grid simulation; ferromagnetic core; finite element model; iSFCL; impedance measurement; inductive superconducting fault current limiter; lumped element circuit model; optimization design; power hardware-in-the-loop measurement; power hardware-in-the-loop testing; ring shielding; second generation high temperature superconducting coated conductor; transient simulation model; wide tape; Circuit faults; Computational modeling; Finite element analysis; High-temperature superconductors; Impedance; Impedance measurement; Integrated circuit modeling; Finite-element analysis (FEA); hardware-in-the-loop simulation; high temperature superconductor (HTS); superconducting fault current limiter (SFCL);
fLanguage :
English
Journal_Title :
Applied Superconductivity, IEEE Transactions on
Publisher :
ieee
ISSN :
1051-8223
Type :
jour
DOI :
10.1109/TASC.2013.2291117
Filename :
6665050
Link To Document :
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