Comments on “Low-Latency Digit-Serial Systolic Double Basis Multiplier over

The digit-serial systolic double basis multiplier architecture proposed in the above paper does not generate the correct multiplication results as it requires more latches to process digits of inputs in appropriate clock cycles. In this comment, we present the corrected architecture and obtain its time and area complexities. More importantly, we show that the claims made by the authors regarding having significantly lower time and area complexities than its counterpart are not valid.