Title :
A Built-In Self-Repair Scheme for 3-D RAMs With Interdie Redundancy
Author :
Che-Wei Chou ; Yu-Jen Huang ; Jin-Fu Li
Author_Institution :
Dept. of Electr. Eng., Nat. Central Univ., Taoyuan, Taiwan
Abstract :
3-D integration using through silicon via is an emerging technology for integrated circuit designs. Random access memory (RAM) is one good candidate for the application of 3-D integration technology. However, yield will be a key challenge for the volume production of 3-D RAMs. In this paper, we present yield-enhancement techniques for 3-D RAMs. An interdie redundancy scheme is proposed to improve the yield of 3-D RAMs. Three stacking flows with respect to different bonding technologies for 3-D RAMs with interdie redundancy are proposed as well. Finally, a built-in self-repair (BISR) scheme is proposed to perform the repair of 3-D RAMs with interdie redundancies. The BISR circuits in two stacked dies can work together to allocate interdie redundancies. Simulation results show that the proposed yield-enhancement techniques can effectively improve the yield of 3-D RAMs.
Keywords :
built-in self test; integrated circuit design; integrated circuit yield; maintenance engineering; microassembling; random-access storage; redundancy; three-dimensional integrated circuits; 3D RAM yield; 3D integration technology; BISR circuits; BISR scheme; bonding technology; built-in self-repair scheme; integrated circuit designs; interdie redundancy scheme; random access memory; stacked dies; three stacking flows; through silicon via; volume production; yield-enhancement techniques; Bonding; Built-in self-test; Maintenance engineering; Random access memory; Redundancy; Registers; Stacking; 3-D integrated circuit (IC); 3-D random access memory (RAM); memory repair; memory testing; through-silicon-via (TSV); yield improvement;
Journal_Title :
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
DOI :
10.1109/TCAD.2012.2222882
