Title :
Fabrication and Testing of a TSV-Enabled Si Interposer With Cu- and Polymer-Based Multilevel Metallization
Author :
Lannon, J. ; Hilton, Adrian ; Huffman, Alan ; Butler, Mairead ; Malta, D. ; Gregory, Chris ; Temple, D.
Author_Institution :
RTI Int., Research Triangle Park, NC, USA
Abstract :
An electrically functional freestanding Si interposer for 3-D heterogeneous integration applications is designed and successfully fabricated. The interposer employs multilevel metallization (MLM) on the frontside of the wafer and Cu-filled through-Si vias (TSVs) and MLM on the backside. The MLM structures use electroplated Cu and polymer dielectrics of the type used in wafer-level packaging. The fabrication flow of the 3-D interposer test vehicle incorporates the formation of TSVs, the deposition and patterning of two routing levels of frontside MLM, wafer thinning, and the deposition and patterning of backside MLM. TSVs 80 μm in diameter, 315 μm in depth, and 80 μm in diameter, 265- μm depth (4:1 or 3:1 aspect ratio, respectively) are demonstrated. The frontside and backside MLM were formed with 3- μm-thick Cu routing layers and 5- μm-thick spin-on dielectric layers. Daisy chains consisting of 528 TSVs connecting the frontside and backside metal layers are tested for electrical continuity. Individual TSV operability exceeds 99.98%. Details of the MLM and TSV process modules, including thermal stabilization of Cu-filled TSVs and process integration required to successfully obtain the high TSV operability, are described.
Keywords :
copper; electroplating; integrated circuit manufacture; integrated circuit testing; metallisation; polymers; silicon; thermal stability; three-dimensional integrated circuits; wafer level packaging; 3D heterogeneous integration applications; 3D interposer test vehicle; Cu; Si; TSV-enabled silicon interposer fabrication; TSV-enabled silicon interposer testing; TSVs; backside metal layer; copper-filled through-silicon vias; daisy chains; electrically functional freestanding silicon interposer; electroplated copper; frontside MLM deposition; frontside MLM patterning; frontside metal layer; polymer dielectrics; polymer-based multilevel metallization; process integration; routing levels; size 265 mum; size 3 mum; size 315 mum; size 5 mum; size 80 mum; spin-on dielectric layers; thermal stabilization; wafer thinning; wafer-level packaging; Annealing; Fabrication; Metallization; Routing; Silicon; Through-silicon vias; Multilevel metallization (MLM); Si interposer; through-Si vias (TSVs);
Journal_Title :
Components, Packaging and Manufacturing Technology, IEEE Transactions on
DOI :
10.1109/TCPMT.2013.2284580