Compact Zero-Temperature Coefficient Modeling Approach for MOSFETs Based on Unified Regional Modeling of Surface Potential

A compact zero-temperature coefficient (ZTC) modeling approach is demonstrated for generic MOSFETs. Instead of manually extracting ZTC points through C-V or I-V data over a range of operating temperatures, the ZTC model marks the cross-over ZTC points by Newton-Raphson solutions to the ZTC voltages based on the compact charge/current models. It calculates the ZTC voltages in the accumulation (V_ztc,sa) and depletion (V_ztc,ds) regions based on the unified regional modeling of surface potential for the gate capacitance at zero drain bias (V_ds=0). It is extended to the ZTC voltage (V_ztc,ds) for gate capacitance in the depletion and saturation regions at any V_ds, and the ZTC voltage (V_ztc) for drain current in the linear and saturation regions at any V_ds. The proposed approach can be adopted to create a process window with constant ZTC contours for different process parameters, such as body doping and gate-oxide thickness at any drain biases. The process windows provide useful information in determining the optimum process parameters and operating voltages for circuit design in ruggedized electronics that operate at high-temperature conditions.