Title :
Depth-Reliability-Based Stereo-Matching Algorithm and Its VLSI Architecture Design
Author :
Der-Wei Yang ; Li-Chia Chu ; Chun-Wei Chen ; Jonas Wang ; Ming-Der Shieh
Author_Institution :
Dept. of Electr. Eng., Nat. Cheng Kung Univ., Tainan, Taiwan
Abstract :
A low-complexity depth-reliability-based stereomatching algorithm and an efficient scanline memory-merging implementation scheme are proposed in this paper. The developed algorithm analyzes the accuracy of disparity results by using simple local window-based methods and preserves reliable information only. A bidirectional depth propagation flow is then adopted to fill the unreliable segments by using reliable information. Moreover, a set of predefined function-specific reliability variables are extracted to further improve depth quality in the occluded and smooth regions, which can reduce 39% bad pixels obtained by applying the basic 7 × 7 window-based matching. The proposed scanline memory-merging scheme along with data prefetching can lead to 32.7% savings on the scanline memory area and relax the requirements of external frame buffer size and bandwidth. Experimental results show that the implemented stereo-matching hardware has a gate count of 223 k including the scanline memory, and can achieve up to 70 frames/s for 480 × 540 resolution (2 × 2 downsampling of FullHD side-by-side 3-D format) with 56 disparity levels.
Keywords :
VLSI; image matching; stereo image processing; VLSI architecture design; bidirectional depth propagation flow; depth reliability based stereo matching algorithm; external frame buffer bandwidth; external frame buffer size; reliable information; scanline memory area; scanline memory merging implementation; simple local window based methods; window based matching; Algorithm design and analysis; Computer architecture; Hardware; Optimization; Reliability; Shape; Very large scale integration; Reliability-based computation; Stereo matching; reliability-based computation.; stereo-matching; window-based sum of absolute differences (SAD) architecture;
Journal_Title :
Circuits and Systems for Video Technology, IEEE Transactions on
DOI :
10.1109/TCSVT.2014.2361419