DocumentCode
1760619
Title
Negative Bias Temperature Instability in p-FinFETs With 45
Substrate Rotation
Author
Moonju Cho ; Ritzenthaler, R. ; Krom, Raymond ; Higuchi, Yuji ; Kaczer, Ben ; Chiarella, T. ; Boccardi, Guillaume ; Togo, Mitsuhiro ; Horiguchi, Naoto ; Kauerauf, T. ; Groeseneken, Guido
Author_Institution
Interuniv. Microelectron. Centre, Leuven, Belgium
Volume
34
Issue
10
fYear
2013
fDate
Oct. 2013
Firstpage
1211
Lastpage
1213
Abstract
Negative bias temperature instability (NBTI) reliability in p-FinFET devices is studied with respect to the silicon substrate orientation. Interface trap density Nit is lower in the 45° rotated devices compared with the 0° rotated devices because of lower density of Si dangling bond at the (100) side walls than the (110) side walls. This improves NBTI reliability in the 45° rotated FinFET devices. Furthermore, we demonstrate that the lower inversion charge density Ninv-exhibited when transitioning from planar to FinFET architecture at 45° rotation-plays an important role in the whole NBTI degradation. NBTI clearly improves in the 45° rotated FinFET devices compared with the planarlike device because of the lower Ninv. Leakage current density analysis is shown as an experimental proof, in addition to simulation results of Cho et al.
Keywords
MOSFET; bonding processes; current density; elemental semiconductors; interface states; leakage currents; semiconductor device reliability; silicon; stability; Interface trap density; NBTI; Si; dangling bonding; leakage current density analysis; negative bias temperature instability; p-FinFET device; planarlike device; reliability; silicon substrate rotation orientation; Degradation; FinFETs; High K dielectric materials; Logic gates; Reliability; Silicon; Substrates; Charge trapping; FinFET; logic device; multigate FET; negative bias temperature instability (NBTI);
fLanguage
English
Journal_Title
Electron Device Letters, IEEE
Publisher
ieee
ISSN
0741-3106
Type
jour
DOI
10.1109/LED.2013.2273361
Filename
6585760
Link To Document