A 2.4 GHz 0.1-Fref-Bandwidth All-Digital Phase-Locked Loop With Delay-Cell-Less TDC

Author

Minyoung Song ; Inhwa Jung ; Pamarti, Sudhakar ; Kim, Chong-Kwon

Author_Institution

Sch. of Electr. Eng., Korea Univ., Seoul, South Korea

Volume

60

Issue

12

fYear

2013

fDate

Dec. 2013

Firstpage

3145

Lastpage

3151

Abstract

An all-digital phase locked loop (ADPLL) with a proposed time-to-digital converter (TDC) which has no delay cell is designed by the 0.13- μm CMOS process. The delay-cell-less TDC (DLTDC) that can suppress device noises and PVT mismatches is essential for wider bandwidth operations. Moreover, sub-gate TDC resolution can be achieved with the proposed DLTDC. A ring-VCO based digitally-controlled oscillator (DCO) which reduces 1/f noise is also proposed to enhance noise performance. The 2 MHz BW ADPLL which occupies 0.42 mm² consumes 12 mA and its measured jitter is 4 psrms at 2.4 GHz.

Keywords

1/f noise; CMOS digital integrated circuits; digital phase locked loops; time-digital conversion; voltage-controlled oscillators; 1/f noise; CMOS; all-digital phase-locked loop; current 12 mA; delay-cell-less TDC; digitally-controlled oscillator; frequency 2.4 GHz; jitter; ring-VCO; size 0.13 mum; time-to-digital converter; Clocks; Delays; Inverters; Phase locked loops; Phase noise; Voltage-controlled oscillators; All-digital PLL (ADPLL); delay-cell-less TDC; low noise VCO; phase-locked loop (PLL); time-to-digital converter (TDC);

fLanguage

English

Journal_Title

Circuits and Systems I: Regular Papers, IEEE Transactions on

Publisher

ieee

ISSN

1549-8328

Type

jour

DOI

10.1109/TCSI.2013.2265975

Filename

6585805