DocumentCode
1761100
Title
Design of ternary clock generator
Author
Yan-Feng Lang ; Ji-Zhong Shen ; Liang Geng ; Mao-Qun Yao
Author_Institution
Dept. of Inf. Sci. & Electron. Eng., Zhejiang Univ., Hangzhou, China
Volume
50
Issue
15
fYear
2014
fDate
July 17 2014
Firstpage
1052
Lastpage
1054
Abstract
A ternary clock generator (TCG) is proposed to settle its shortage. The TCG is implemented at the switch level with a simple structure of 24 MOS transistors and simulated at the layout level using the HSPICE software with TSMC 0.18 μm CMOS technology, showing that it works properly. The analyses show that the proposed TCG not only can output a ternary clock of high quality, meeting the clock´s design requirements, but also can be fabricated with standard CMOS technology.
Keywords
CMOS integrated circuits; clocks; integrated circuit design; HSPICE software; MOS transistors; TSMC CMOS technology; clocks design requirements; layout level; size 0.18 mum; standard CMOS technology; switch level; ternary clock generator;
fLanguage
English
Journal_Title
Electronics Letters
Publisher
iet
ISSN
0013-5194
Type
jour
DOI
10.1049/el.2014.1590
Filename
6856338
Link To Document