Title :
Analysis and Design of a 14.1-mW 50/100-GHz Transformer-Based PLL With Embedded Phase Shifter in 65-nm CMOS
Author :
Yue Chao ; Luong, Howard C. ; Zhiliang Hong
Author_Institution :
Dept. of Electron. & Comput. Eng., Hong Kong Univ. of Sci. & Technol., Hong Kong, China
Abstract :
A low-voltage and low-power 50/100-GHz transformer-based phase-locked loop (PLL) is implemented in a 65-nm CMOS technology. Consuming only 14.1 mW from a 0.6/1.2-V supply, the PLL measures phase noise of -90/ -84 dBc/Hz at 100-kHz offset and -94/ -88 dBc/Hz at 1-MHz offset at 49.7/99.4 GHz while occupying a core chip area of 0.39 mm2. Moreover, with an embedded phase shifter, the PLL output phase can be shifted by a 360 ° range with an average resolution of 3.9 ° and amplitude variation less than ±0.1 dB, which makes it suitable for phased-array transceivers.
Keywords :
CMOS integrated circuits; field effect MIMIC; millimetre wave phase shifters; phase locked loops; CMOS; amplitude variation; core chip area; embedded phase shifter; frequency 50 GHz to 100 GHz; low-power PLL; low-voltage PLL; phase noise; phased-array transceivers; power 14.1 mW; size 65 nm; transformer-based PLL; transformer-based phase-locked loop; voltage 0.6 V to 1.2 V; Logic gates; Phase locked loops; Phase noise; Phase transformers; Tuning; Voltage-controlled oscillators; CMOS; frequency divider; millimeter-wave (mm-Wave); phase shifter; phase-locked loop (PLL); phased array; voltage-controlled oscillator (VCO);
Journal_Title :
Microwave Theory and Techniques, IEEE Transactions on
DOI :
10.1109/TMTT.2015.2407364
