1T Capacitor-Less DRAM Cell Based on Asymmetric Tunnel FET Design

Author

Biswas, Arnab ; Ionescu, Adrian M.

Author_Institution

Nanolab, Ecole Polytech. Fed. de Lausanne, Lausanne, Switzerland

Volume

3

Issue

3

fYear

2015

fDate

42125

Firstpage

217

Lastpage

222

Abstract

In this work we propose and demonstrate the use of a Tunnel FET (TFET) as capacitorless DRAM cell based on TCAD simulations and experiments. We report more experimental results on Tunnel FETs implemented as a double-gate (DG) fully-depleted Silicon-On-Insulator (FD-SOI) devices. The Tunnel FET based DRAM cell has an asymmetric body and a partial overlap of the top gate (L_G1) with a total overlap of the back gate over the channel region (L_G2). A potential well is created by biasing the back gate (V_G2) in accumulation while the front gate (V_G1) is in inversion. Holes from the p+ source are injected by the forward-biased source/channel junction and stored in the electrically induced potential well. Programming conditions and related transients are reported and the role of temperature is investigated.

Keywords

DRAM chips; field effect transistors; silicon-on-insulator; technology CAD (electronics); tunnel transistors; DG FD-SOI device; TCAD simulation; TFET; asymmetric tunnel field effect transistor design; back gate overlap; capacitor-less DRAM cell; channel junction; channel region; double-gate fully-depleted silicon-on-insulator device; forward-biased source junction; potential well; Current measurement; Discharges (electric); Electric potential; Field effect transistors; IEEE Electron Devices Society; Logic gates; Random access memory; 1T/0C; Capacitorless memory; DRAM; Tunnel FET;

fLanguage

English

Journal_Title

Electron Devices Society, IEEE Journal of the

Publisher

ieee

ISSN

2168-6734

Type

jour

DOI

10.1109/JEDS.2014.2382759

Filename

6990484