Title :
Immediate Calibration of Operational Amplifier Gain Error in Pipelined ADCs Using Extended Correlated Double Sampling
Author :
Hafiz, O.A. ; Xiaoyue Wang ; Hurst, Paul J. ; Lewis, Stephen H.
Author_Institution :
Dept. of Electr. & Comput. Eng., Univ. of California, Davis, Davis, CA, USA
Abstract :
This paper introduces extended correlated double sampling (ECDS) as a new gain-calibration technique in pipelined analog-to-digital converters (ADCs). The proposed calibration simultaneously improves the effective dc gain and increases the maximum output swing of the opamps with given overdrive voltages. Furthermore, ECDS is immediate, thus avoiding the long convergence time associated with many background calibration schemes. This characteristic makes it desirable for applications where the ADC is on only briefly, such as wireless sensor networks (WSNs). An 11-bit 40-MS/s prototype pipelined ADC has been fabricated in 0.25-μm CMOS to demonstrate the proposed calibration technique. The active die area is 3.8 mm2 , and the analog power dissipation is 85 mW from a 2.5-V supply. With a 72-kHz input frequency, ECDS improves signal-to-noise-and-distortion ratio from 40.1 to 63.4 dB and spurious-free dynamic range from 41.8 to 75.7 dB.
Keywords :
CMOS analogue integrated circuits; analogue-digital conversion; calibration; operational amplifiers; CMOS process; DC gain; WSN; analog power dissipation; background calibration schemes; bit rate 40 Mbit/s; extended correlated double sampling; operational amplifier gain error calibration; pipelined ADC; pipelined analog-to-digital converters; power 85 mW; signal-to-noise-and-distortion ratio; size 0.25 mum; voltage 2.5 V; wireless sensor networks; word length 11 bit; Calibration; Capacitance; Capacitors; Clocks; Gain; Noise; Transistors; Analog-to-digital converter (ADC); CMOS analog integrated circuits; calibration; correlated double sampling (CDS); correlated level shifting (CLS); finite gain; gain error; pipelined ADC; time-aligned correlated double sampling; time-shifted correlated double sampling;
Journal_Title :
Solid-State Circuits, IEEE Journal of
DOI :
10.1109/JSSC.2012.2230545