In Situ Power Gating Efficiency Learner for Fine-Grained Self-Adaptive Power Gating

A low-power in situ learner circuit is presented to characterize the tradeoff between leakage saving and transition energy overhead in power gating (PG). A self-adaptive PG scheme is demonstrated that utilizes the learner circuit to adaptively invoke PG only when leakage saving is more than the transition energy overhead. A 130-nm test chip demonstrates functionality of the learner circuit and its application to adaptive PG under varying process, temperature, and idle signal pattern.