DocumentCode :
1762160
Title :
A Loop Gain Optimization Technique for Integer- N TDC-Based Phase-Locked Loops
Author :
Ting-Kuei Kuan ; Shen-Iuan Liu
Author_Institution :
Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan
Volume :
62
Issue :
7
fYear :
2015
fDate :
42186
Firstpage :
1873
Lastpage :
1882
Abstract :
This paper presents a loop gain optimization technique for integer- N digital phase-locked loops with a time-to-digital converter. Due to noise filtering properties, a phase-locked loop has an optimal loop gain which gives rise to the best jitter performance, taking into account external and internal noise sources. By using the loop gain optimization technique, the digital phase-locked loops can automatically attain this loop gain in background to minimize the jitter. Theoretical analysis is presented. The stability issue and the impact of loop latency are also discussed. Finally, the analysis is compared to behavioral simulations with good agreement.
Keywords :
circuit noise; digital phase locked loops; jitter; time-digital conversion; external noise source; integer-N digital phase-locked loop; internal noise source; jitter minimization; loop gain optimization technique; loop latency; noise filtering property; stability issue; time-to-digital converter; Clocks; Jitter; Noise; Optimization; Phase locked loops; Quantization (signal); Timing; Digital phase-locked loop; discrete-time domain analysis; jitter minimization; loop gain optimization; loop latency; stability; time-to-digital converter;
fLanguage :
English
Journal_Title :
Circuits and Systems I: Regular Papers, IEEE Transactions on
Publisher :
ieee
ISSN :
1549-8328
Type :
jour
DOI :
10.1109/TCSI.2015.2423793
Filename :
7122940
Link To Document :
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