• DocumentCode
    1762185
  • Title

    Digital Analog Design: Enabling Mixed-Signal System Validation

  • Author

    Byong Chan Lim ; Mao, James ; Horowitz, Mark ; Ji-Eun Jang ; Jaeha Kim

  • Author_Institution
    Stanford Univ., Stanford, CA, USA
  • Volume
    32
  • Issue
    1
  • fYear
    2015
  • fDate
    Feb. 2015
  • Firstpage
    44
  • Lastpage
    52
  • Abstract
    This paper proposes a method to validate mixed-signal circuits and systems using procedures similar to those used for digital model of the transistor implementation, the suitability of the design can be judged. The significance of this work is how these models are constructed and compared, and how this information is managed using existing digital CAD tools. Since analog test program content is typically compiled based on the specifications in the data sheet for the analog circuit, often without the benefit of fault coverage information, there are frequent redundancies in the overall test process.
  • Keywords
    electronic design automation; integrated circuit design; integrated circuit modelling; integrated circuit testing; mixed analogue-digital integrated circuits; transistor circuits; analog circuit; analog test program content; digital CAD tools; digital analog design; digital model; fault coverage information; mixed-signal circuits; mixed-signal system validation; Analog circuits; Formal verification; Linear systems; Mathematical model; Mixed analog digital integrated circuits; System-on-chip; Testing; Analog validation; SystemVerilog; behavioral modeling; design methodology; equivalence checking; event-driven simulation; linear abstraction; test vector generation;
  • fLanguage
    English
  • Journal_Title
    Design & Test, IEEE
  • Publisher
    ieee
  • ISSN
    2168-2356
  • Type

    jour

  • DOI
    10.1109/MDAT.2014.2361718
  • Filename
    6917049