DocumentCode
1762288
Title
Wide-range (25 ns) and high-resolution (48.8 ps) clock phase shifter
Author
Guoying Wu ; Yu, Bei ; Ping Gui ; Moreira, Paulo
Author_Institution
Southern Methodist Univ., Dallas, TX, USA
Volume
49
Issue
10
fYear
2013
fDate
May 9 2013
Firstpage
642
Lastpage
644
Abstract
A wide-range (25 ns), high-resolution (48.8 ps) clock phase shifter developed and fabricated using a 0.13 μm CMOS technology is presented. To achieve both wide range and high resolution with good linearity while minimising area and power consumption, a coarse-fine two-step phase-shifting structure is proposed. A delay-locked loop with an unconventional clock input setup is used in the fine-shifting stage to ahieve the high resolution. Test results show that the standard deviations of the differential nonlinearity and integral nonlinearity are 4.7 ps and 4.3 ps, respectively.
Keywords
CMOS logic circuits; clocks; delay lock loops; phase shifters; CMOS technology; coarse-fine two-step phase shifting structure; delay-locked loop; fine-shifting stage; high-resolution clock phase shifter; power consumption; size 0.13 mum; time 25 ns; time 48.8 ps; unconventional clock input setup; wide-range clock phase shifter;
fLanguage
English
Journal_Title
Electronics Letters
Publisher
iet
ISSN
0013-5194
Type
jour
DOI
10.1049/el.2012.4274
Filename
6528800
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